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III 2650 ASSEMBLER LANGUAGE
INTRODUCTION ........................................93
LANGUAGE ELEMENTS ..................................97
Characters ...........................................97
Symbols ............................................97
Constants ...........................................97
Multiple Constant Specifications ............................99
Expressions ..........................................99
Special Operators ......................................100
SYNTAX .............................................101
Fields ..............................................101
Symbols ............................................102
Symbolic References ....................................102
Symbolic Addressing ....................................102
PROCESSOR INSTRUCTIONS ...............................105
DIRECTIVES TO THE 2650 ASSEMBLER .......................106
THE ASSEMBLY PROCESS .................................115
Assembly Listing ......................................118
IV 2650 SIMULATOR
INTRODUCTION .......................................123
SIMULATOR OPERATION .................................124
General ............................................124
Simulated Processor State. ................................124
Simulated Memory .....................................125
Simulated Input/Output Instructions .........................125
USER COMMANDS .....................................126
General. ............................................126
Command Formats .....................................127
Command Descriptions ..................................130
SIMULATOR DISPLAY (LISTING) ...........................139
V APPENDIXES
APPENDIX A MEMORY INTERFACE EXAMPLE ...............147
APPENDIX B I/O INTERFACE EXAMPLE ....................148
APPENDIX C INSTRUCTIONS, ADDITIONAL INFORMATION .....149
APPENDIX D INSTRUCTION SUMMARY ....................151
APPENDIX E SUMMARY OF 2650 INSTRUCTION MNEMONICS ....160
APPENDIX F NOTES ABOUT THE 2650 PROCESSOR ...........162
APPENDIX G ASCII AND EBCDIC CODES ....................163
APPENDIX H COMPLETE ASCII CHARACTER SET .............164
APPENDIX I POWERS OF TWO TABLE .....................165
APPENDIX J HEXADECIMAL-DECIMAL CONVERSION TABLES ...166
APPENDIX K COMMAND SUMMARY .......................171
APPENDIX L ERROR MESSAGES .........................172
APPENDIX M SIMULATOR RESTRICTIONS ..................174
APPENDIX N SIMULATOR RUN PREPARATION ...............174
Copyright 1975-Printed in USA. Signetics Corporation reserves the right to make changes in the products described in this book in order to improve design or performance. Signetics Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement.
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III 2650 ASSEMBLER LANGUAGE
INTRODUCTION ........................................93
LANGUAGE ELEMENTS ..................................97
Characters ...........................................97
Symbols ............................................97
Constants ...........................................97
Multiple Constant Specifications ............................99
Expressions ..........................................99
Special Operators ......................................100
SYNTAX .............................................101
Fields ..............................................101
Symbols ............................................102
Symbolic References ....................................102
Symbolic Addressing ....................................102
PROCESSOR INSTRUCTIONS ...............................105
DIRECTIVES TO THE 2650 ASSEMBLER .......................106
THE ASSEMBLY PROCESS .................................115
Assembly Listing ......................................118
IV 2650 SIMULATOR
INTRODUCTION .......................................123
SIMULATOR OPERATION .................................124
General ............................................124
Simulated Processor State. ................................124
Simulated Memory .....................................125
Simulated Input/Output Instructions .........................125
USER COMMANDS .....................................126
General. ............................................126
Command Formats .....................................127
Command Descriptions ..................................130
SIMULATOR DISPLAY (LISTING) ...........................139
V APPENDIXES
APPENDIX A MEMORY INTERFACE EXAMPLE ...............147
APPENDIX B I/O INTERFACE EXAMPLE ....................148
APPENDIX C INSTRUCTIONS, ADDITIONAL INFORMATION .....149
APPENDIX D INSTRUCTION SUMMARY ....................151
APPENDIX E SUMMARY OF 2650 INSTRUCTION MNEMONICS ....160
APPENDIX F NOTES ABOUT THE 2650 PROCESSOR ...........162
APPENDIX G ASCII AND EBCDIC CODES ....................163
APPENDIX H COMPLETE ASCII CHARACTER SET .............164
APPENDIX I POWERS OF TWO TABLE .....................165
APPENDIX J HEXADECIMAL-DECIMAL CONVERSION TABLES ...166
APPENDIX K COMMAND SUMMARY .......................171
APPENDIX L ERROR MESSAGES .........................172
APPENDIX M SIMULATOR RESTRICTIONS ..................174
APPENDIX N SIMULATOR RUN PREPARATION ...............174
Copyright 1975-Printed in USA. Signetics Corporation reserves the right to make changes in the products described in this book in order to improve design or performance. Signetics Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement.
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CHAPTER I INTRODUCTION
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INTRODUCING THE 2650 FAMILY
"5-VOLT SYSTEM REDUCES SYSTEM COSTS"
"2650 PUTS THE INTERFACE ON THE CHIP...NOT ON THE CIRCUIT BOARD" "POWERFUL INSTRUCTION SET PROVIDES LOWER COST SYSTEMS"
The greatly increased sophistication and rising production costs of today's logic systems force the system designer to use every available resource in order to economically produce his system. In keeping with this cost reduction goal, Signetics has developed a powerful general purpose integrated microprocessor called the 2650. The first Signetics microprocessor, in conjunction with Signetics MOS and Bipolar memory and interface product lines, offers the system designer a viable and attractive alternative to the hard-wired approach to system design. For many applications, the system designer can use this general purpose microprocessor and standard memory and interface circuits to implement systems with lower cost than the hardwired logic approach without sacrificing performance.
By using the 2650 and compatible products, the system designer can obtain two other major benefits of microcomputer systems. These benefits are greatly enhanced system flexibility and minimized design or modification cycles compared with the hard-wired logic approach.
The requirements of the majority of applications for integrated microprocessors (logic replacement, and control functions) have defined a general set of processor parameters based on system and device economies, ease of use. and speed requirements.
These characteristics include:
Single chip Eight bit parallel structure
Fixed instruction set TTL compatibility
In addition to these characteristics, the design of the 2650 has been optimized around three generalized objectives:
Lowest system cost Capable of a wide range
Ease of useof applications
The optimum technology choice for implementing these features is the: low threshold ion-implanted N-Channel silicon gate process. This process has matured in the past few years, providing a combination of high density, ' low threshold voltage, moderate speed and good manufacturing yields. Using this technology, a total of 576 bits of ROM, approximately 250 bits of register and about 900 logic gates are used to implement the processor function on the 2650 chip.
The instruction set consists of 75 instructions, of which about 40% consists of arithmetic instructions. This class contains the Boolean, arithmetic, and compare operations, each of which may be executed using any one of eight addressing modes. Another 30% of the instruction set consists of branch instructions which incorporate six addressing modes. The remaining 30% of the instruction set includes, amoung others, I/O instructions, instructions for performing operations on the two status registers, a decimal adjust instruction and the HALT instruction.
Utilizing multiple addressing modes greatly increases coding efficiency, allowing functions to be performed using fewer instructions than less powerful machines. The resulting reduction in routine execution time and memory capacity requirements directly translates into improved system performance and reduced memory cost. In this way the powerful instruction set and addressing modes of the 2650 allow a significant reduction in the memory required to perform a given function, resulting in sizeable system cost savings without sacrificing performance.
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FEATURES OF THE 2650 FAMILY
2650 FAMILY APPROACH
Low System Cost
— Low cost N-Channel products
— Intrinsic advantages of single 5V supply
— Uses standard low cost memories
— Low cost interfacing
Ease of Use
— Easy interfacing
— Conventional instruction set
— Ease of programming
Wide Range of Applications
— General purpose capability
— Powerful architecture
— Powerful instruction set
— Flexible
— Expanding family of devices
FEATURES OF THE MICROPROCESSOR Basic 2650 Processor Characteristics
Single chip 8-bit processor
Signetics low threshold double ion-implanted
silicon gate N-Channel technology
Single +5V power supply
Low power consumption: 525 mW maximum
Single phase TTL-compatible clock
Static operation: no minimum clock fi'equency
Clock frequency: 1.25MHz maximum
Cycle time: 2.4/us minimum
Standard 40 pin DIP
2650 Interfaces
TTL compatible inputs, outputs — no external
resistors required
Tri-state bus outputs for multiprocessor and
direct memory access systems 1» Asynchronous (handshaking) memory and I/O
interface
Accepts wide range of memory timing
Interfaces directly with industry standard memories
Powerful control interface
Single-bit direct serial I/O path
Parallel 8-bit I/O capability
2650 Processor Architecture
8-bit bidirectional tri-state data bus Separate tri-state address bus 32,768-byte addressing range Internal 8-bit parallel structure Seven 8-bit addressable general purpose registers Eight-level on-chip subroutine return address stack
Program status word for flexibility and enhanced processing power
Single-level hardware vectored interrupt capability
Interrupt service routines may be located anywhere in addressable memory Separate adder for fast address calculation
2650 Instruction Set
General purpose instruction set with substantial capabilities in arithmetic, character manipulation and control and I/O processing
* Fixed instruction set
* 75 instructions
Up to eight addressing modes
True indexing with optional auto increment/
decrement
One, two or three byte instructions 1 One- and two-byte I/O instructions
Selective test of individual bits
Powerful instruction set and addressing modes minimize memory requirements
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FEATURES OF COMPATIBLE PRODUCTS 2602, 2606, 1K RAMs
* Completely static operation
* N-Channel silicon gate technology
* 1024 X 1 organization (2602) 256 X 4 organization (2606)
* Single +5V power supply
* 200mW typical power dissipation
* Maximum access time: I/us : 2602 750ns : 2606 650ns : 2602-2 500ns : 2602-1, 2606-1
* TTL-compatible « Tri-state outputs " Data I/O bus (2606 only) Standard 16 pin DIP
2608 8K ROM
Completely static operation
N-Channel silicon gate technology
1024 X 8 organization
Single +5V power supply
400mW maximum power dissipation
650ns maximum access time
TTL compatible
Tri-state outputs
Standard 24 pin DIP
8T26 Quad Transceiver
Schottky TTL technology
Four pairs of bus drivers/receivers
Separate drive and receive enable lines
Tri-state outputs
Low current pnp inputs
High fan out — driver sinks 40mA 20ns maximum propagation delay Standard 16 pin DIP
8T31 8-bit Bidirectional Port
Schottky TTL technology
Two independent bidirectional busses
Eight bit latch register
Independent read, write controls for each bus
Bus A overrides if a write conflict occurs
Register can be addressed as a memory location via Bus B Master Enable
30ns maximum propagation delay
Low input current: SOOjuA
High fan out — sinks 20mA
Standard 24 pin DIP
8T95/6/7/8 Hex Buffers/Inverters
Schottky TTL technology
Six buffers or inverters per package
Non-inverting (8T95, 8T97) or Inverting (8T96, 8T98)
Buffered control lines
Tri-state outputs
Low current pnp inputs
Standard 16 pin DIP
82S115/123/129 PROMs
Schottky TTL technology
Single +5V power supply
« 32 X 8 organization (82S123)
256 X 4 organization (82S129)
512 X 8 organization (82S115)
Field programmable (Nichrome)
On-chip storage latches (82S115 only)
Low current pnp inputs
Tri-state outputs
35ns typical access time
Standard 24 pin DIP (82S115)
Standard 16 pin DIP (82S123, 82S129)
(See Appendix for additional products and data
sheets.)
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PROCESSOR HARDWARE DESCRIPTION
ARCHITECTURE GENERAL DESCRIPTION
A block diagram of the processor is shown in Figure 1. The first, second, and third bytes of instructions are read into the processor on the data bus and loaded into the Instruction Register, Holding Register, and Data Bus Register, respectively. The instructions are decoded through a combination of ROM and random logic.
The ALU performs arithmetic. Boolean, and combinatorial shifting functions. It operates on eight bits in parallel and utilizes carry-look-ahead logic. A second adder is used to increment the instruction address register and to calculate operand addresses for the indexed and relative addressing modes. This separate address adder allows complex addressing modes to be implemented with no increase in instruction execution time.
The General Purpose Register Stack and the Subroutine Return Address Stack are implemented with static RAM cells. The Register Stack consists of seven 8-bit registers. The Subroutine Stack can contain eight 15-bit addresses, thereby allowing eight levels of subroutine nesting. Placing the Subroutine Stack on the chip allows efficient ROM-only systems to be implemented in some applications. Separate 15-bit Instruction Address and Operand Address Registers and provided. The 2650 is an 8-bit binary processor with BCD capability. See Figure 2 for a diagram of the 2650 registers as seen by the programmer.
PROGRAM STATUS WORD. -
The Program Status Word (PSW) is a major feature of the 2650 with greatly increases its flexibility and processing power. The PSW is a special purpose register within the processor that contains status and control bits.
It is divided into two bytes called the Program Status Upper (PSU) and Program Status Lower (PSL). The PSW bits may be tested, loaded, stored, preset, or cleared using the instructions which affect the PSW. The bits are utilized as follows:
PSUO, 1,2 - SP - Pointer for the Return Address Stack.
PSU5— II — Used to Inhibit recognition of additional Interrupts.
PSU6— F — Flag is a latch directly driving the flag output.
PSU7— S — Sense equals the state of the sense input.
PSLO— C — Carry stores any carry from the high-order bit of the ALU.
PSL1— COM — Compare determifes if a logical or arithmetic comparison is to be made.
PSL2— OVF — Overflow is set if a two's complement overflow occurs.
PSL3— WC — With Carry determines i4- the carry is used in arithmetic and rotate instructions.
PSL4— RS — Register Select identifies which bank of 3 GP registers is being used.
PSL5— IDC — Inter Digit Carry stores the bit-3-to-bit-4 carry in arithmetic operations.
PSL6, 7 — CC — Condition Code is affected by compare, test and arithmetic instructions.
INTERRUPT HANDLING CAPABILITY
The 2650 has a single level hardware vectored interrupt capability. When an interrupt occurs, the 2650 finishes the current instruction and sets the
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Interrupt Inhibit bit in the PSW. The processor then executes a Branch to Subroutine Relative to location Zero (ZBSR) instruction and sends out Interrupt Acknowledge and Operation Request signals. On receipt of the INTACK signal the interrupting device inputs an 8-bit address, the interrupt vector, on the data bus. The relative and relative indirect addressing modes combined with this 8-bit address allow interrupt service routines to begin at any addressable memory location.
Figure 1. BLOCK DIAGRAM
SUBROUTINE RETURN ADDRESS STACK 18 « 15 RAM)
GENERAL PURPOSE REGISTERS
INSTRUCTION ADDRESS REGISTER
PAGE CONTROL
'2 SP, SP0 PSU
-STACK POINTER
- UNUSED
' INTERRUPT INHIBIT
- FLAG
- SENSE
- CARRY BIT — LOG1CAL/AH1TH COMPARE
- OVERFLOW BIT . WITH/WITHOUT CARRY . REGISTER BANK SELECT . INTEHDIGITCARRY CONDITION CODE
PROGRAM STATUS WORD
NOTE: Not all internal registers are shown.
Figure 2. MAJOR 2650 REGISTERS
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INTERFACING
INTRODUCTION TO INTERFACING WITH THE 2650
Five key concepts have been incorporated in the 2650 to make interfacing easy and inexpensive. The extent to which these concepts have been incorporated in the Signetics 2650 provides unique benefits of system density and low cost to the system designer.
1. SINGLE 5V POWER SUPPLY
Low threshold double ion-implanted Silicon Gate N-Channel MOS technology is used to allow operation from one +5V power supply with resultant cost savings and improved reliability. This reduces power consumption significantly compared with the multi-power supply approach.
2. INTERFACE CIRCUIT COMPATIBILITY
The 2650 inputs and outputs are specified to be compatible with widely available, standard, low cost logic families such as TTL, CMOS and Low-power STTL. This includes the single phase clock input which saves the cost of high level multiphase clock driver circuitry. Bus outputs are tri-state and capable of driving one 7400 TTL load or four 74LS loads. The 2650 is capable of driving several loads of pnp-buffered STTL inputs. Many MSI, Interface and Memory LSI circuits (for example, in Signetics 82SOO and 8TOO series) have these low current pnp inputs and are recommended for use in 2650 microcomputer systems. See Table 1 for DC characteristics of the 2650.
3. USE OF STANDARD MEMORIES
One of the major 2650 design achievements is to operate efficiently in a system using industry standard memories, for example 1024 X 1 and 256 X 4 N-channel RAMs and 1024 X 8 N-Channel ROMs These standard memories are widely available and used in volume with corresponding low cost. Non-standard memories, particularly those produced by only one manufacturer will be less available, run in lower volume and often cost 2 to 3 times as much per bit as industry standard products. The 2650 operates successfully with memories of any access time, due to the completely asynchronous interface that is provided for this purpose. Memories which respond in less than 0.8 microseconds allow the processor to operate at maximum speed.
4. NO SPECIAL INTERFACE PRODUCTS
Similarly, another major achievement is to operate efficiently in a system using no special I/O products. This approach avoids the problems of a system requiring high cost specialized components with restricted availability.
TABLE 1. PRELIMINARY 2650 DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOLPARAMETERTEST CONDITIONSMINMAXUNIT
ILIInput Load CurrentV|N = 0 to 5.25V10MA
!LOHOutput Leakage CurrentADREN, DBUSEN = 2.2V, VOUT = 4V10MA
!LOLOutput Leakage CurrentADREN, DBUSEN = 2.2V, VOUT " 0.45V10MA
icePower Supply Currentvcc = 5.25V, TA = o"c100mA
VILInput Low-0.60.8V
VIHInput High2.2VCGV
VOLOutput LowIOL = 1-6 mA0.00.45V
VOHOutput HighIOH = -100 MA2.4VCC-0.5V
CINInput CapacitanceV|N = ov10PF
COUTOutput CapacitanceVOUT = ov10pF
Conditions: TA ^ 0"C to 70"C,
= 5V .'. 5%
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5. POWERFUL MEMORY AND I/O INTERFACE
The following features characterize the memory and I/O interfaces:
Both memory and input/output may operate in a completely asynchronous fashion. Consequently, devices operating at any speed up to the maximum data transfer rate may be connected without buffering. External latching of data from these interfaces is not required.
Data paths are driven with tri-state buffers, allowing multiprocessor and Direct Memory Access (DMA) configurations to be designed.
Eight-bit data paths communicate data in parallel.
One- and two-byte I/O instructions provide maximum flexibility and efficiency when interfacing with I/O devices.
SENSE ADR12 <— ADR11 <— ADR10<~ ADR9 <— ADR8 <— ADR7<~
ADR4 < ADR3< ADR2 < ADR1 < ADRO<
ADREN -
RESET-
TfijTREQ -
ADR14-0/C<
ADR13-E/NE <
1 w40—— > FLAG
239— ovcc
338£ —— CLOCK
437£ —— PAUSE
536£ —— OPACK
635£ —— RUN /WATT
734—— > INTACK
833£ — > DBUSO
g32£ —— > DBUS1
265031i —— > DBUS2
1130c — > DBUS3
1229—— > OBUS4
1328e~> DBUS5
1427£ — > OBUS6
1526^— > OBUS7
16 1725 24—— DBUSEN —— ^ OPREQ
1823—— > R/W
1922—— > WRP
2021—— O GND
FigureS. PIN CONFIGURATION
\ , _
PIN CONFIGURATION AND INTERFACE SIGNAL DEFINITION
Refer to Figure 3 for the 2650 pin configuration. Signals are defined as follows:
ADRO-ADR12 — The low order 13 bits of address for memory access are on these pins. ADRO-ADR7 are also used in two-byte I/O instructions. These outputs are tri-state buffers controlled by ADREN.
ADR13-E/NE — This multiplexed output signal delivers the ADR13 address bit when M/IO is in the M phase or discriminates between Extended and Non-Extended I/O instructions when M/IO is in the I/O phase.
ADR14-D/C — Address 14 or Data/Control is a multiplexed output signal. This pin delivers the ADR14 address bit when M/IO is in the M phase or discriminates between Data and Control I/O instructions when M/IO is in the I/O phase.
ADREN— Address Bus Enable is an input providing the external control for the ADRO-ADR12 tri-state buffer drivers.
DBUSO-DBUS7 - This is the 8-bit, bidirectional tri-state bus over which most data is communicated into or out of the processor.
DBUSEN— Data Bus Enable is an input that controls the tri-state buffer drivers for DBUSO to DBUS7.
OPREQ— Operation Request is an output signal that informs external devices that the information on other output pins is valid. ..-.-., , - ...i »-
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OPACK— Operation Acknowledge is an input which is used by
external devices to end an I/O or memory signaling
sequence. M/IO— Memory/Input-Output. This output informs external
devices whether Memory or Input/Output functions are
being performed. R/W— This output signal describes an I/O or memory operation
as Read or Write, and defines whether the bidirectional
DBUS is transmitting or receiving. WRP— This Write Pulse is generated during write sequences and
may be used to strobe memory or I/O devices. SENSE— Is an input, independent of the other I/O signals, that
provides a direct input to the processor. FLAG— This pin provides a direct output signal that is completely
independent of the other I/O signals. INTREQ— Interrupt Request. This input is used by external devices
to force the processor into the Interrupt sequence.
INTACK— Interrupt Acknowledge is the signal used by the processor to inform external devices that it has entered an
interrupt sequence. PAUSE— Pause is used to temporarily stop the processor at the end
of the current instruction. It may stop processing for an
indefinite length of time and is available to use for DMA
(Direct Memory Access). RUN/WAIT — Informs external circuits as to the Run/Wait status of the
2650 processor.
RESET— Is an input used to cause the 2650 to begin processing
from a known state. CLOCK— This is the only clock input to the processor. It accepts
standard TTL levels. VCC- +5V power. GND — The logic and power supply ground for the processor.
2650 TIMING
The clock input to the 2650 provides the basic timing information that the processor uses for all its internal and external operations. The clock rate determines the instruction execution time, except to the extent that external memories and devices slow the processor down. The maximum clock rate of the standard 2650 is 1.25 Megacycles (one clock period is 800ns minimum). One unique feature of the 2650 is that the clock frequency may be slowed down to DC, allowing complete timing flexibility for interfacing. This feature permits single stepping the clock which can greatly simplify system checkout. It also provides an easy method to halt the processor. Each 2650 cycle is comprised of three clock periods. Direct instructions require either 2, 3, or 4 processor cycles for execution and, therefore, vary from 4.8 to 9.6/us in duration.
A timing diagram for a memory read cycle is shown in Figure 4. OPREQ (Operation Request) is the master control signal that coordinates all operations external to the processor. When true, OPREQ indicates that other output signals are valid. During a memory read cycle M/IO is in the M (Memory) state and R/W is in the R (Read) state. The address lines and the control lines become valid before OPREQ rises. The data to be read may be returned anytime after OPREQ becomes valid. An OPACK (Operation Acknowledge) should accompany the read data from the memory. The Data and OPACK signals should remain valid for 50 ns after OPREQ falls.
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INPUT/OUTPUT INTERFACE
The 2650 microprocessor has a set of versatile I/O instructions and can perform I/O operations in a variety of ways. One- and two-byte I/O instructions are provided, as well as a special single-bit I/O facility. The I/O modes provided by the 2650 are designated as Data, Control, and Extended I/O.
Data or Control I/O instructions are one byte long. Any general purpose register can be used as the source or destination. A special control line indicates if either a Data or Control instruction is being executed. Extended I/O is a two-byte read or write instruction. Execution of an extended I/O instruction will cause an 8-bit address, taken from the second byte of the instruction, to be placed on the low order eight address lines. The data, which can originate or terminate with any general purpose register, is placed on the data bus. This type of I/O can be used to simultaneously select a device and send data to it.
Memory reference instructions that address data oxitside of physical memory may also be used for I/O operations. When an instruction is executed, the address may be decoded by the I/O device rather than memory.
MEMORY INTERFACE
The memory interface consists of the address bus, the 8-bit data bus and several signals that operate in an interlocked or handshaking mode.
The Write Pulse signal is designed to be used as a memory strobe signal for any memory type. It has been particularly optimized to be used as the Chip Enable or Read/Write signal for the Signetics 2602 and 2606 RAMs.
INTERFACING - A MINIMAL SYSTEM EXAMPLE
The 2650 has been designed for low cost, easy interfacing, which is dramatically illustrated by a minimal system configuration shown in Figure 5. This system has a Teletype interface, 1024 bytes of ROM, and 256 bytes of RAM, yet requires only seven (7) standard integrated circuit packages. The ROM can contain a bootstrap loader and I/O driver programs for the Teletype. Other programs could reside in ROM or be read into RAM via the Teletype. An alternative to the 2608 N-Channel MOS ROM is the 82S115 Bipolar PROM which offers a 512 X 8 organization. Only one +5-volt power supply is required for this system. The advantages of conceptual simplicity and minimum system costs of the 2650 approach will be obvious to the system designer, particularly when compared to alternative microprocessor products.
NOTES:
1 ONE 'SVSUPPLV SEVEN 1C PACKAGES
1. -CMOS RECEIVER USED FOR HIGH NOISE
Figure 4. MEMORY READ CYCLE TIMING
Figure 5. SEVEN PACKAGE MINIMAL SYSTEM
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INSTRUCTION SET
It may be seen from examination of the 2650 instruction set that there are many powerful instructions which are all easily understood and are typical of larger computers. There are one-, two-, and three-byte instructions as a result of the multiplicity of addressing modes. See Table 2 for a complete listing and Figure 6 for instruction formats.
Automatic incrementing or decrementing of an index register is available in the arithmetic indexed instructions. All of the branch instructions except indexed branching can be conditional.
Register-to-register instructions are one byte; register-to-storage instructions are two or three bytes long. The two-byte register-to-memory instructions are either immediate or relative addressing types.
TABLE 2. INSTRUCTION SET
MNEMONICOP CODEFORMAT*DESCRIPTION OF OPERATIONAFFECTSCYCLES
7000 0001ZLoad Register ZeroCC (Note 1)2
r000 00121Load ImmediateCC (Note 1 12
LODR000 0102RLoad RelativeCC (Note 1)3
A000 01 13ALoad AbsoluteCC (Note 114
z1 1 0 0001ZStore Register Zero (r^to)CC (Note 1)2
STRR110 0102RStore Relative-3
(A1100113 AStore Absolute4
L Z100 ooo12Add to Register Zero w/wo CarryC, CC (Note 1), 1DC, OVF2
1100 00121Add Immediate w/wo CarryC, CC (Note 1), IDC, OVF2
ADD>A1000102RAdd Relative w/wo CarryC, CC (Note 1), IDC, OVF3
A100 01 13AAdd Absolute w/wo CarryC, CC (Note 1), IDC, OVF4
z101 00012Subtract from Register Zero w/wo BorrowC, CC (Note 1), IDC, OVF2
SUB1101 00121Subtract Immediate w/wo BorrowC, CC (Note 1). IDC, OVF2
R101 0102RSubtract Relative w/wo BorrowC, CC (Note 1), IDC, OVF3
A101 0113ASubtract Absolute w/wo BorrowC, CC (Note 1), IDC, OVF4
DAR100 1011ZDecimal Adjust RegisterCC (Note 2)3
1Z01000012AND to Register Zero (r^tO)CC (Note 1)2
AND1010 00121AND ImmediateCC (Note 1) : 2
r010 0102RAND RelativeCC (Note 1)3
[ A0100113AAND AbsoluteCC (Note 1)4
Z01 1 00012Inclusive OR to Register ZeroCC (Note 1)2
IOR1011 00121Inclusive OR ImmediateCC (Note 1)2
R011 0102RInclusive OR RelativeCC (Note 1)3
A011 0113AInclusive OR AbsoluteCC (Note 1)4
f001 0001ZExclusive OR to Register ZeroCC (Note 112
FOR *001 00121Exclusive OR ImmediateCC (Note 1) , - .2
t UnR001 0102RExclusive OR RelativeCC (Note 1)3
A001 0113AExclusive OR AbsoluteCC (Note 1)4
2111 00012Compare to Register Zero Arithmetic/LogicalCC (Note 3)2
COMI111 00121Compare Immediate Arithmetic/LogicalCC (Note 4)2
R111 0102RCompare Relative Arithmetic/LogicalCC (Note 4)3
A111 Oil3ACompare Absolute Arithmetic/LogicalCC (Note 414
RRR010 1001ZRotate Register Right w/wo CarryC, CC, IDC, OVF2
RRL1 1 0 1 001ZRotate Register Left w/wo CarryC, CC, IDC, OVF2
R000 1102RBranch On Condition True Relative_3
BCTA000 1 1 13BBranch On Condition True Absolute-3
ppcR100 1102RBranch On Condition False Relative3
DUrA100 1 113BBranch On Condition False Absolute- .3
BRNR010 1102RBranch On Register Non-Zero Relative_3
A010 1113BBranch On Register Non-Zero Absolute. .... \3
R 1 RR110 1102RBranch On Incrementing Register Relative_3
DinA1101113BBranch On Incrementing Register Absolute_3
Dpi RR111 1102RBranch On Decrementing Register Relative_3
DLJ r\A111 1113BBranch On Decrementing Register Absolute-3
ZBRR100 110 112ERZero Branch Relative, Unconditional_3
BXA1 00 1 1 1 113EBBranch Indexed Absolute, Unconditional3
(Note 5}
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SUPPORT
DOCUMENTATION
The complete manual set is available in a durable 3-ring binder. The binder contains the Hardware Specifications, the Assembler Language Manual, the Software Simulator Manual, and a section called System Application Notes. Our update service provides customers with new application notes and updates to the manual set.
The Hardware Specification Manual includes a detailed description of the instruction set, the pin-outs, the AC and DC electrical characteristics, the Input/Output and memory interface signals with timing diagrams, the internal processor organization, and other useful information.
The Assembler Language Manual describes how to write programs in the 2650 symbolic assembly language, the pseudo-ops, and how to assemble a 2650 program. Additional information is presented on how to use the assembler program, how to interpret the output listings and how to load object modules.
The Simulator Manual describes the nature of the simulation program, how to write simulation commands and how to interpret the simulation output.
System Application Notes are included to help the user design with the 2650 processor. These notes present detailed technical information on various subjects of interest and apply to either programming, hardware configuration, or system concepts. This section will continue to grow.
I/O Device Selection Methods A Minimal System Configuration
Examples of Application Notes are:
Serial I/O for the 2650
Memory Interfaces,. :
How to use the Decimal .<.' .
Adjust instruction
r>s . .' .. ~ .
SOFTWARE SUPPORT' ''
Signetics-developed software is available to both the batch processing user and the timesharing user. The Batch Assembler and Batch Simulator are written in standard FORTRAN and may be compiled and executed on most medium to large scale computer systems. Because of the modular design used, it is expected that many minicomputer users will also be able to utilize these programs. The main features of the programs are listed in Tables 3 and 4.''''
Signetics has also made the Batch Assembler, Batch Simulator and Interactive Simulator available on several international timesharing networks for those customers who wish to run these programs using a timesharing service.
When a customer chooses to follow the timesharing approach, he can also make use of the interactive version of the 2650 Simulator. With the Inter-
TABLE 3. ASSEMBLER FEATURES
2-Pass Assembler
* Diagnostic error messages
* Symbolic addressing including
forward references Constant generation
*' Pseudo-ops to aid programming Free format source code
TABLE 4. SIMULATOR FEATURES
Cycle Counter for timing estimates Instruction fetch break points Operand fetch break points Trace facilities Snapshot dumps Patching facility
Statistical information generated Easy-to-use command language Optionally selected start and end addresses Dynamic changes of simulated registers Optionally simulates ROM-RAM environment
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active Simulator the software designer can utilize his timesharing terminal to dynamically alter his program and effectively reduce his program development time.
The Signetics 2650 Symbolic Assembly Language has been modeled after other assembly languages; because of this, the assembler is easy to learn and to use.
The Simulator programs are designed to aid the user in testing and correcting his programs. This approach is an alternative to dedicating hardware development tools to one or two programmers or designers for program development. The Simulator allows users to simulate the execution of programs without utilizing a processor. The Simulator utilizes the object module produced by the Assembler as input, and through use of appropriate simulator commands, can display and/or alter the internal registers of the simulated 2650 processor and the simulated memory contents.
The programs are. usually delivered delivered on IBM compatible magnetic tape "mini-reels". All programs are in FORTRAN source code as card image records.
A growing Program Library is available to Signetics microprocessor users. We encourage users to submit all non-proprietary programs to Signetics to add to the program library so that we may make them available to other users.
PROTOTYPING HARDWARE PROTOTYPING CARD
In order to develop a product using the Signetics 2650 microprocessor, both hardware and software must be designed. Recognizing that the basic needs of many of our customers for prototyping systems will be similar, Signetics has designed a prototyping card containing a basic microcomputer system. This card provides a starting point for the development of hardware interfaces while simultaneously providing a tool for software checkout.
The first Signetics prototyping card consists of a 2650 processor, ROM memory containing a loader and editor, RAM memory for program storage before committing to PROM or ROM, a TTY interface for easy access, a crystal-controlled clock and two input and output ports (8 bits each).
SYSTEM COMPATIBLE FAMILIES
The 2650 has been designed to interface directly with industry standard logic and memory families, particularly 7400 and 74LSOO logic families, TTL compatible 5V NMOS memories (Signetics' 2600 series) and bipolar memories (Signetics' 8200 and 82SOO series). Many interface circuits in the 8TOO family are particularly useful for constructing interfaces in 2650 systems.
Other logic families including 8200 TTL. 82SOO STTL and 4000 CMOS are compatible with the 2650. See Table 5.
TABLE 5. SYSTEM COMPATIBLE FAMILIES
Logic 7400, 8200-TTL
74LSOO-TTL-LS
82SOO-STTL
4000-CMOS .--,..
Memory 2500-PMOS ,. . , .
2600-NMOS ..'
7400, 8200-Bipolar TTL .. .
82SOO-Bipolar STTL
Interface 8TOO-TTL, STTL
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