Below: A closer view showing the individual beads. I believe this plane would have been hand-made. Later planes were much smaller and more even, suggesting they were formed by machines. I have a later example and will post that here when I get a chance to take some photographs (I did that, see below).

The whole plane. There are 4 sections, each has 33 beads across and 64 down, for 2048 bits per section and 8192 bits for the board. The 33rd bit would have been the parity bit, leaving 4 lots of 8. IBM computers at that time used a code called EBCDIC with 8 bits per character. A ‘word’ was 32 bits wide, hence the organisation.

Electrically, core memory is fairly simple. Each row and each column has a wire that goes through each bead in the row or column, obviously they cross at right angles at each bead. To read or write a bit into the bead one half of the current necessary to flip the magnetic state of the ferrite bead is passed through the appropriate row and column wires. Where they cross, and only there, the ferrite bead receives sufficient energy to set its state to ‘0’ or ‘1’ depending on the direction of the current. The magnetic flux in the bead was clockwise for one state and anticlockwise for the other.

A single ‘sense’ wire snakes its way through every bead, that’s the wire you can see on the left and the right with the loops in it. To read the state of a bit, the bit is reset to the ‘0’ state. If the bit is already ‘0’, no change occurs in the magnetic flux of the ferrite bead. If however, the bit had been ‘1’, resetting it to ‘0’ flips it’s state and this causes a change in the magnetic flux. The ‘sense’ wire, which passes through the centre of the ferrite bead, gets a small current induced in it by this change. That current is amplified and read as a ‘1’ by the logic surrounding the memory plane.

If the bit is a ‘1’ the logic creates a further memory cycle to write a ‘1’ back to the bit. Obviously this cycle is unncessary if the bit was a ‘0’.

Unlike RAM memory today, ferrite core memory does not require power to keep it’s data intact. It was quite common to turn a machine off for service or storage and some considerable time later (even months) on turn-on the core memory was still fully intact and the machine could be run without going through the ‘boot loader’ process.

A trade-off with core memory was the amount of heat generated from the relatively high currents required to switch the magnetic flux. The early core modules were bathed in oil to keep them cool. I am told by the previous owner, who used the machine these planes came from, that the original memory bank cost the customer over $1m USD.

My early experience was with DEC PDP 8/e processors. The system at the Reserve Bank in Wellington had 16 K words of core memory organised as 4 banks of 4k 12 bit words. It also had a drum memory, a very unusual storage medium even at the time. More on that elsewhere in due course, and no, I don’t have a real drum memory.

Back with IBM computers, and just to prove that not much really changes in the computer industry, there used to be a joke circulating that if the computer was slow, it just needed the bird call ‘mawcaw, mawcaw’ to fix it. (pronounced more-core, more-core).

The later bank of core memory I found is quite different, much smaller and a lot more regular. It is formed by two folding panels, the logic is on the outside, the core planes on the inside. This is the front view. The label reads “electronic memories NANOII 4Kx18/8Kx9CORE STACK ASSY S/03461” The part number is 910711-A01, the serial number is 31051, it lists c/n T8910711A and d/c 3073. The little sticker in the top left hand corner has “910711-AO1 31051 REV H 11-1-73” and EM277 on a diagonal. The inside of the panels shows the serial number to have A on the end of the left hand panel and a B on the end for the right hand panel.

And the back view

When the panels are unfolded, the inside shows the planes of ferrite beads. Each board is about 300mm or 12 inches wide. A very large number of very fine wires bridge the hinge area.

One panel. I assume the configuration is 8 bits plus parity, per panel as shown.

One of the individual sections. The writing says “F/L 30089-M60”

These things are rather small. This is the same section as above but with a ruler to show the size. An inch is 2.54 centimetres or 25 mm. My digital camera cannot resolve the individual beads. They would be less than 0.5 mm across.

The packing density on this panel is so high that I assume it was produced at the end of the life-cyle for core- memory. I do not recall the PDP 8/e core memory ferrite beads to be as small as this one, but unfortunately I was unable to buy a plane that was offered recently.

Doing some calculations, it was 1972 when I was working in Wellington with the PDP 8’s, so it is feasible that this 1973 plane was the end of its line. By the time I was back in Christchurch at the University of Canterbury in 1973, the PDP 8 was being replaced by the PDP 11 which (from memory here) did not use core memory.

Update: I was finally able to purchase an actual PDP-8 core memory module, as pictured below.